The present invention generally relates to a semiconductor memory device, and more particularly relates to an electrically erasable and programmable read-only memory (EEPROM).
A flash EEPROM, or flash memory, which includes a plurality of nonvolatile memory cells, each having a control gate, a floating gate for the storage of charges thereon, a drain and a source, and can collectively erase stored data on a predetermined block basis, is well known in the art. A flash memory is used as a built-in memory for a microcomputer, for example. In recent years, the bit width of data transmitted in a microcomputer tends to increase.
A flash memory for erasing stored data using a block of memory cells connected to a single word line as a minimum unit is described in Japanese Laid-Open Publication No. 6-29499. The flash memory includes: an erase unit block including a number N (where N is an integer) of nonvolatile memory cells; a word line connected to the respective control gates of the number N of nonvolatile memory cells; a source line connected to the respective sources of the number N of nonvolatile memory cells; and a number N of bit lines each connected to the drain of associated one of the number N of nonvolatile memory cells. In a read cycle, a positive high potential is applied by a word line driver to one terminal of the word line, a ground potential is applied by a source line driver to one terminal of the source line, and a positive low potential is applied by a read amplifier to all of the number N of bit lines. In such a configuration, nonuniformity in erasure characteristics of memory cells within a unit block can be advantageously suppressed. It should be noted that data bits stored in all of the number N of nonvolatile memory cells, of which one erase unit block is made up, are read simultaneously in this configuration.
In this prior art flash memory, current flows from the number N of bit lines through at least some of the number N of nonvolatile memory cells having lower threshold voltages into the source line and is ultimately concentrated at the source line driver during a read cycle. Assume all of the number N of nonvolatile memory cells discharge the current into the source line and the level of the current discharged by each nonvolatile memory cell into the source line is 60 .mu.A. In such a case, if N is equal to 256, then the current flowing through the source line exceeds 15 mA.
During an erase or program cycle, potentials may be applied to a nonvolatile memory cell in any of various fashions. With regard to a so-called "NOR-type" cell, a positive high potential and a ground potential are applied to a bit line and a source line, respectively, during a program cycle. Even then, current is also concentrated at a source line driver.
In order to adopt a sub-micron rule for the purpose of implementing an array of memory cells with an even higher density, it is not preferable to allow such a large current as exceeding 15 mA to flow through a source line, which is composed of a diffused line and an aluminum line backing the diffused line and has a width of 0.5 .mu.m, for example. In such a case, the performance of the device deteriorates because the program/read speed decreases due to a large voltage drop in the source line. In addition, a fatal problem, seriously affecting the reliability thereof, possibly happens, that is, the disconnection of the source line owing to electromigration.